Design-Reuse5d
SPI Master / Slave Controller w/FIFO (APB Bus)
The Digital Blocks DB-SPI-MS is a Serial Port Interface (SPI) Controller Verilog IP Core supporting both Master/Slave SPI Bus transfers. The DB-SPI-MS contains an AMBA AXI, AHB, or APB Bus Interface ...
Design-Reuse5d
System Packet Interface (SPI) 4.2 IP Core
Kaushal Buch, Tarang Popat, Rahul Jain, eInfochips Ltd.
Bloomberg L.P.1d
Swiss Exchange Swiss Performance Index
Connecting decision makers to a dynamic network of information, people and ideas, Bloomberg quickly and accurately delivers business and financial information, news and insight around the world ...
Yahoo Finance6d
ASX SPI 200 Index Futures (AP17H.AX)
As of 16 March at 11:58:26 am AEDT. Market open.
GitHub5d
can-bus
Pac-Man for LandTiger Board is a Pac-Man game implementation for the LandTiger development board (ARM Cortex-M3). It features joystick controls, AI-controlled ghosts, sound effects, CAN bus ...