Impact on DRAM Performance The DDR3 column granularity is 64 Bytes ... in a bussed topology but at a time only one module can be accessed via chip select pin. Inside the DIMM, the DQ is point-to-point ...

The TCI DDR PHY is a high-performance, scalable system using a radically new architecture that continuously and automatically adjusts each pin individually ... and PHY Vref and DRAM Vref settings.